1. Field of the Invention
This invention relates to a driver circuit for a matrix type color television panel in which a color television picture is displayed by a time sharing drive.
2. Description of the Prior Art
The matrix type color television panel described herein is designed so that the complete picture comprises picture elements divided in, for example, X and Y directions and each having at least one color picture element, for example, red (R), green (G) and blue (B). Each color picture element is given an electric signal to provide a color television display. For display materials, liquid crystal, fluorescent, electrochromic, ferroelectric materials and the like are available. Since this invention is concerned with a method of applying picture signals, it will be described hereinafter through the use of an example of liquid crystal.
The structure of a liquid crystal driver circuit for giving a color television picture display by a conventional time sharing drive is shown in a block diagram of FIG. 1. A color separation circuit 1-1 separates picture signals into R, G and B color signals and sends the R color signal to an analog-to-digital (A/D) converter 2-R, the G color signal to an A/D converter 2-G, and the B color signal to an A/D converter 2-B, respectively. Also, a synchronizing separation circuit 1-2 separates the incoming picture signals into synchronizing signals (horizontal synchronizing signals and vertical synchronizing signals) and sends them into a control circuit 3.
The A/D converter 2-R (G, B) transmits the R (G, B) color signal to a digital line memory 4-R (G, B). The digital line memory 4-R (G, B) stores one line of R (G, B) color signals and sends the data in parallel to a digital latch circuit 5-R (G, B) in synchronism with the signals of the control circuit 3, for example, during the flyback period of horizontal scanning lines. While holding the data during the horizontal scanning period, the digital latch circuit 5-R (G, B) sends the data to pulse width modulating circuits 6-1-R (G, B) to 6-n-R (G, B) each of which is also used as a column electrode driver.
Corresponding to the digital data from the digital latch circuit 5-R (G, B), the modulating circuits 6-1-R (G, B) to 6-n-R (G, B) modulate the output pulse width so as to control an effective voltage to be applied to column electrodes 8-1-R (G, B) to 8-n-R (G, B) for a liquid crystal color panel. The control circuit 3 is synchronized with the incoming synchronizing signals and gives a data shift order to the digital line memory 4-R (G, B), a latch order to the digital latch circuit 5-R (G, B) and a control order to a line electrode driver 7. The line electrode driver 7 selects one of line electrodes 9-1 to 9-m in accordance with the signals of the control circuit 3.
Next, to show the IC structure for driving one of the column electrodes 8-1-R (G, B) to 8-n-R (G, B), an enlarged circuit diagram of the digital line memory 4-R, digital latch circuit 5-R, and pulse width modulating circuit 6-1-R corresponding to the column electrode 8-1-R of FIG. 1 is given in FIG. 2. The A/D converter 2-R of FIG. 1 is for four bits. This number of bits is minimum for satisfying the quality of the display. In FIG. 2, 4-R' denotes a first column of the digital line memory 4-R of FIG. 1, and 5-R' denotes a first column of the digital latch circuit 5-R of FIG. 1. The first column 4-R' of the digital line memory 4-R comprises four D type flip-flops 12. Each of outputs 11-1 to 11-4 of the A/D converter 2-R of FIG. 1 is applied to each of the flip-flops 12 and stored therein in accordance with a data shift order pulse applied to a data shift order pulse line 10.
11-1' to 11-4' are output lines respectively for the next column. The digital latch circuit 5-R' also comprises four D type flip-flops 13. While the outputs of the digital line memory 4-R are held in the D type flip-flops 13 during the horizontal scanning period in accordance with a latch order pulse applied to a latch order pulse line 17, they are sent to a four-bit to 16-bit decoder 14 of the pulse width modulating circuit 6-1-R. The decoder 14 decodes the incoming four-bit signals and selects one of sixteen transmission gates 15 at its outputs to connect one of sixteen modulating signal lines 16-l to 16-16 to a column electrode drive line 18, thus providing an intermediate modulating display.
The above-mentioned drive portion for the one-column electrode needs about 150 gates for the CMOS structure. For example, for 300 column electrodes, the column electrode drive portion needs a large number of gates, i.e. 45,000 gates. An increase in the number of gates decreases the IC yield and increases the area of IC chips and power consumption. Furthermore, from the standpoint of the entire driver circuit, A/D converters required for each R, G and B color signal bring about disadvantages such as the increased cost, large power consumption, large occupied volume of the driver circuit and the like. That is to say, because of the great number of gates and the necessity of A/D converters, the conventional circuit has disadvantages of high cost, large mounting area and high power consumption.